Speakers and Speeches Information
Title:The CUDA to FPGA Compiler
Abstract:GPUs and FPGAs are popular accelerators in heterogeneous systems for speeding up compute intensive kernels of scientific, imaging and simulation applications. GPUs can execute thousands of concurrent threads, while FPGAs provide customized concurrency for highly parallel kernels. However, exploiting the parallelism available in these applications is currently not a push-button task. Often the programmer has to expose the application’s fine and coarse grained parallelism by using special APIs. CUDA is such a parallel-computing API that is driven by the GPU industry and is gaining significant popularity. In this work, we adapt the CUDA programming model into a new FPGA design flow called FCUDA, which efficiently maps the coarse and fine grained parallelism exposed in CUDA onto the reconfigurable fabric. FCUDA enables to use a common front end language to target heterogeneous computing with both GPUs and FPGAs. FCUDA supports three types of computing platforms: SoC, NoC and manycore with hierarchical bus, providing different compute acceleration solutions depending on the unique features of the computing tasks and targeted FPGA hardware itself.
Bio: Dr. Deming Chen obtained his BS in computer science from University of Pittsburgh, Pennsylvania in 1995, and his MS and PhD in computer science from University of California at Los Angeles in 2001 and 2005 respectively. He joined the ECE department of University of Illinois at Urbana-Champaign in 2005 and has been a full professor in the same department since 2015. His current research interests include system-level and high-level synthesis, computational genomics, nano-systems design and nano-centric CAD techniques, GPU and reconfigurable computing, and hardware security. Dr. Chen is a technical committee member for a series of conferences and symposia. He is or has been an associated editor for TCAD, TODAES, TVLSI, TCAS-I and II, JCSC, and JOLPE. He obtained the Achievement Award for Excellent Teamwork from Aplus Design Technologies in 2001, the Arnold O. Beckman Research Award from UIUC in 2007, the NSF CAREER Award in 2008, and six Best Paper Awards for ASPDAC'09, SASP'09, FCCM'11, SAAHPC'11, CODES+ISSS'13, and ICCAD'15. He is included in the List of Teachers Ranked as Excellent in 2008. He received the ACM SIGDA Outstanding New Faculty Award in 2010, and IBM Faculty Award in 2014 and 2015. He is a senior member of IEEE and the Donald Biggar Willett Faculty Scholar.
Title: Secure consumer UAVs
Abstract: Consumer unmanned aerial vehicles (UAVs) have become popular in recent years. While their extreme mobility enables exciting new applications, they also raise various security concerns. We analyzed several popular UAVs and discovered a variety of vulnerabilities. After illustrating examples of these vulnerabilities, I will discuss the challenges in securing the software and hardware of UAVs, and propose potential directions.
Bio: Dr. Hao Chen received his Ph.D. at the Computer Science Division at the University of California, Berkeley in 2004. Since then, he has been on the faculty of the Department of Computer Science at the University of California, Davis. He won the National Science Foundation CAREER award in 2007, and UC Davis College of Engineering Faculty Award in 2010. His research has been featured in both print and broadcast media, such as the New York Times, the Sacramento Bee, and the Capitol Public Radio. He co-founded and chaired the IEEE Mobile Security Technologies in 2012.
Title: Deep Learning Hardware Accelerators
Abstract: In this talk, I am going to review the brief history of deep learning hardware accelerators, and discuss potential issues in future development of this field. In addition, I would like to introduce Cambricon Ltd., a new startup set up by the Chinese Academy of Sciences.
Bio: Tianshi Chen is the founder and CEO of Cambricon Technologies Corporation Limited, and an associate professor with the Institute of Computing Technology, Chinese Academy of Sciences, Beijing, China. He received the BS degree in mathematics from the Special Class for the Gifted Young, University of Science and Technology of China (USTC), Hefei, China, in 2005, and the PhD degree in computer science from the School of Computer Science, USTC, in 2010. His current research interests include computer architecture and computational intelligence. Together with his Chinese and international collaborators, he received ASPLOS2014 Best Paper Award and MICRO2014 Best Paper Award for DianNao-family neural network accelerators. He was a recipient of an NSFC excellent young scholar award in 2015, a recipient of an Intel early career faculty award in 2014, and a recipient of the China Computer Federation Distinguished Doctoral Dissertation Award in 2011.
Title: Why FinFET and What Next?
Abstract: FinFET provides a path for continued channel length reduction by continued scaling of the body (fin) thickness. It also significantly reduces voltage/power with the ideal ~60mV/decade turn on/off. It, however, does not provide a path for continued voltage reduction. For that we must look to bold changes of the transistors.
Bio: Prof. Hu is a member of the US National Academy of Engineering, the Chinese Academy of Sciences, and Academia Sinica. Prof. Hu has just been selected to receive the National Medal of Technology and Innovation, which is the highest honor for achievement and leadership in advancing science and technology in the USA.
Dr. Chenming Hu has been called the Father of 3D Transistor for developing the FinFET in 1999. Intel is the first company to use FinFET in 2011 production calling it the most radical shift in semiconductor technology in over 40 years. Other most advanced semiconductor companies will use FinFET in 2014. The world's largest technology association IEEE called him "Microelectronics Visionary" when presenting him the 2009 Nishizawa Medal for "achievements critical to producing smaller yet more reliable and higher-performance integrated circuits". 2011 Asian American Engineer of the Year Award cited his industry-standard transistor model "used in designing IC products with cumulative sales of many hundreds of billions of dollars". 2013 Kaufman Award noted his "tremendous career of creativity and innovation that fueled the past four decades of the semiconductor industry". US Semiconductor Industry Association lauded his research leadership for "advancement of the electronics industry and of our national economy".
Title: Bringing heterogeneous computing to the cloud
Abstract: With diminishing returns on investments in semiconductor technology and the first indications that multicore alone is not likely to allow us to maintain historical system-level performance growth rates, we must now look at heterogeneous architectures to pick up the slack. This presentation will cover some of the new interfaces in the IBM Power 8, Power 8 + NVlink and Power 9 processors intended to make it easier to create high-performance and efficient heterogeneous server systems. We will discuss how the technology can be used to create more efficient compute, networking, and storage and show a few application examples. Finally we will discuss the "Supervessel" cloud (ptopenlab.com), built by the IBM China Research Laboratory where these ideas are being put into practice.
Bio: H. Peter Hofstee was born in the Netherlands and received his Doctorandus in theoretical physics from the University of Groningen, The Netherlands, in 1988. In 1994 he earned his PhD from California Institute of Technology (Caltech). Peter is currently a distinguished research staff member at the IBM Austin Research Laboratory, USA, and a part-time professor in Big Data Systems at Delft University of Technology, Netherlands. Peter is best known for his contributions to Heterogeneous computing as the chief architect of the Synergistic Processor Elements in the Cell Broadband Engine processor used in the Sony Playstation3, and the first supercomputer to reach sustained Petaflop operation. After returning to IBM research in 2011 he has focused on optimizing the system roadmap for big data, analytics, and cloud, including the use of accelerated compute. His early research work on coherently attached reconfigurable acceleration on POWER7 paved the way for the new coherent attach processor interface on POWER8.Peter is an IBM Master Inventor with more than 100 issued patents and a member of the IBM Academy of Technology.
Title: Integrated THz Electronics: High-Power On-Chip Radiation and Large-Scale Terahertz Microsystems
Abstract: Research in the terahertz regime has experienced a few rounds of waves driven alternatively by new application opportunities and key enabling hardware technolgies. Since the 0.17-THz spark gap oscillator in 1923, early THz sources had enabled fundamental physic studies in THz and inter-stellar dust spectroscopy. The needs from later demonstrations, such as non-ionizing imaging and point-to-point communication, in return motivated the development of THz quantum cascade laser, III-V semiconductor components, etc. During the past decade, integrated circuits in silicon has witnessed a rapid increase in operation frequency, leading to an interesting contention on whether these low-cost chips could revolutionize the future sensing and communication infrastructures. Fortunately, skeptics are greatly eased by the dramatic performance improvement of silicon THz sources: the radiated power has increased by five orders of magnitude from the first source (reported in 2008) to our latest radiator array (reported in 2015). The research area is now calling for a new wave of applications to move forward.
In this talk, I will first introduce our efforts across device engineering, nonlinear theories and circuit-electromagnetics integration, in order to push the fundamental limits of silicon devices. By synthesizing multi-mode waves inside a compact electromagnetic structure, our circuits not only maximize the device efficacy, but also perform multiple functions simultaneously. Using such approach, a 320-GHz SiGe transmitter generates a record 3.3-mW radiated power and for the first time demonstrates fully-integrated phase-locking capability in silicon THz radiators. Next, I will present the new opportunities enabled by building large-scale THz microsystems. This will be illustrated by a prototype of a fully-integrated THz imaging chipset with heterodyne detection and digital beam forming (a work in collaboration with Cornell University and STMicroelectronics). Our other THz works in CMOS, such as a THz pulse generator and a Schottky-diode focal-plane array, will be briefly described. Lastly, we will also discuss other opportunities that large-scale silicon microsystems will open up.
Bio: Professor Ruonan Han received his Ph.D. degree in electrical and computer engineering from Cornell University in 2014. Prior to that, he received his B.Sc. degree in microelectronics from Fudan University in 2007 and M.Sc. degree in electrical engineering from the University of Florida in 2009. He worked as a summer intern at Rambus Inc. in 2012. In 2014, he was appointed as an assistant professor by the Department of Electrical Engineering and Computer Science at Massachusetts Institute of Technology. He is also a core faculty member in the Microsystem Technology Laboratories at MIT.
The research of Prof. Han has focused on millimeter-wave and terahertz integrated circuits and microsystems. His group aims to revolutionize the sensing technologies in biomedical diagnosis, homeland security, and industrial quality control. His research also targets at key challenges from the next-generation wireless/wireline communications. Prof. Han was awarded the E. E. Landsman (1958) Career Development Chair Professorship in 2014. He was also the recipient of the IEEE Solid-State Circuits Society (SSCS) Pre-Doctoral Achievement Award, the IEEE Microwave Theory and Tech. Society (MTT-S) Graduate Fellowship Award, the Best Student Paper Award (2nd) at 2012 IEEE RFIC symposium, the ECE Innovation Award and the Director’s Best Thesis Award at Cornell University.
Title: Energy efficient computing: One more reason to tear down those walls
Abstract: For a long time, performance was the sine qua non of microprocessors, and everything else took a back seat. In 1971, the Intel 4004 ran at 106 KHz, 20 years later the Pentium chip ran at 66 MHz, and today, various chips run at more than 3 GHz. It was fair game to add any feature one wished to the microarchitecture, measure its performance and not worry about how much energy is consumed or how much heat has to be removed. As expected, the energy needed to maintain higher and higher performance kept growing. Finally, we hit a wall wherein the energy consumption is so high that we are not able to sustain our requirement for higher performance in light of the cost of concomitant energy. Thus the problem: Keep on driving performance, while at the same time not requiring any more energy. The question is how to make it happen, and who gets to try to do it. I believe the answer lies in the transformation hierarchy, a concept I came up with more than 30 years ago. I hope to show that if we tear down the walls that exist around each level of the transformation hierarchy and instead allow engineers to understand all the levels, and importantly to leverage this understanding, we can continue to build more powerful microarchitectures without increasing energy cost.
Bio: Yale Patt is Professor of Electrical and Computer Engineering and the Ernest Cockrell, Jr. Centennial Chair in Engineering at The University of Texas at Austin. He enjoys equally teaching the 400 student, required Intro to Computing course to freshmen, teaching graduate students, and directing the research of six PhD students in high performance computer implementation. He has, for more than 50 yeasr, combined an active research program with extensive consulting and a strong commitment to teaching. The focus of his research is geneally five to ten years beyond what industry is considering at that point in time. His rationale has always been that he does not do revenue shipments, preferring to produce knowledge that will be useful to future revenue shipments, and more importantly, graduate who will design those future products.
He has won numerous awards. To name a few, the 2016 Benjamin Franklin Medal in Computer and Cognitive Science, the 2013 IEEE Computer Society Harry H. Goode Memorial Award, the 2011 IEEE B. Ramakrishna Rau Award, the 1999 IEEE W.W. McDowell Award and the 1995 IEEE Emannuel R. Piore Medal. He is a Fellow of both the IEEE and the ACM, and a member of the National Academy of Engineering.
Title:Efficient Statistical Validation of Machine Learning Systems for Autonomous Driving
Abstract: Today’s automotive industry is making a bold move to radically transform the conventional mechanical vehicle to a smart electronics system. A modern automobile is now equipped with a powerful computing platform to run multiple machine learning algorithms for environment perception (e.g., pedestrian detection) and motion control (e.g., vehicle stabilization). These machine learning systems must be highly robust with extremely small failure rate in order to ensure safe and reliable driving. In this presentation, I describe a novel statistical methodology to efficiently validate a machine learning system, including algorithm, software and hardware. In particular, a Markov Chain Monte Carlo algorithm is developed to test the given machine learning system and estimate the rare failure rate with a minimal amount of input data. As such, the validation cost is minimized. A traffic sign detection system will be used as the test case to demonstrate the efficacy of the proposed methodology.
Bio: Prof.Xin Li is currently an Associate Professor in the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, PA. In 2005, he co-founded Xigmix Inc. to commercialize his PhD research, and served as the Chief Technical Officer until the company was acquired by Extreme DA in 2007. In 2011, Extreme DA was further acquired by Synopsis (Nasdaq: SNPS). From 2009 to 2012, he was the Assistant Director for FCRP Focus Research Center for Circuit & System Solutions (C2S2), a national consortium of 13 research universities (CMU, MIT, Stanford, Berkeley, UIUC, UMich, Columbia, UCLA, among others) chartered by the U.S. semiconductor industry and U.S. Department of Defense to work on next-generation integrated circuit design challenges. From 2014 to 2015, he was the Assistant Director for the Center for Silicon System Implementation (CSSI), a CMU research center with 20 faculty members working on integrated circuits and systems. His research interests include integrated circuit, signal processing and data analytics.
Dr. Xin Li was an Associate Editor of IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems (TCAD), ACM Trans. on Design Automation of Electronic Systems (TODAES), IEEE Design & Test (D&T), and Journal of Low Power Electronics (JOLPE). He was the Guest Editor for IEEE TCAD, IEEE TNANO, IEEE TBD, IEEE D&T, IEEE JETCAS, ACM TCPS, ACM JETC and VLSI Integration. He served on the Executive Committee of ACM Special Interest Group on Design Automation (SIGDA), the IEEE Systems, Man, and Cybernetics Society Technical Committee on Cybernetics for Cyber-Physical Systems (TCCCPS), and the IEEE Computer Society Technical Committee on VLSI (TCVLSI). He was the General Chair of ISVLSI and FAC, and the Technical Program Chair of CAD/Graphics. He also served on the ACM/SIGDA Outstanding PhD Dissertation Award Selection Committee, the IEEE TTTC E. J. McCluskey Best Doctoral Thesis Selection Committee, the IEEE Outstanding Young Author Award Selection Committee, the Executive Committee of ISVLSI, GLSVLSI and iNIS, and the Technical Program Committee of DAC, ICCAD, ITC, ISVLSI, FAC, CAD/Graphics, ASICON and VLSI. He received the NSF Faculty Early Career Development Award (CAREER) in 2012, the IEEE Donald O. Pederson Best Paper Award in 2013, the Best Paper Award from Design Automation Conference (DAC) in 2010, two IEEE/ACM William J. McCalla ICCAD Best Paper Awards in 2004 and 2011, and the Best Paper Award from International Symposium on Integrated Circuits (ISIC) in 2014.
Title: The Coming of Age of Microfluidics: EDA Solutions for Enabling Biochemistry on a Chip
Abstract: This talk offers attendees an opportunity to bridge the semiconductor ICs/system industry with the biomedical and pharmaceutical industries. This talk will first describe emerging applications in biology and biochemistry that can benefit from advances in electronic “biochips”. The presenters will next describe technology platforms for accomplishing “biochemistry on a chip”, and introduce the audience to both the droplet-based "digital" microfluidics based on electrowetting actuation and flow-based “continuous” microfluidics based on microvalve technology. Next, the presenters will describe system-level synthesis includes operation scheduling and resource binding algorithms, and physical-level synthesis includes placement and routing optimizations. In this way, the audience will see how a “biochip compiler” can translate protocol descriptions provided by an end user (e.g., a chemist or a nurse at a doctor’s clinic) to a set of optimized and executable fluidic instructions that will run on the underlying microfluidic platform. The problem of mapping a small number of chip pins to a large number of array electrodes will also be covered. Finally, sensor feedback-based cyberphysical adaptation will be covered.
Bio: Tsung-Yi Ho received his Ph.D. in Electrical Engineering from National Taiwan University in 2005. He is a Professor with the Department of Computer Science of National Tsing Hua University, Hsinchu, Taiwan. His research interests include design automation and test for microfluidic biochips and nanometer integrated circuits. He has presented 9 tutorials and contributed 9 special sessions in ACM/IEEE conferences, all in design automation for microfluidic biochips. He has been the recipient of the Invitational Fellowship of the Japan Society for the Promotion of Science (JSPS), the Humboldt Research Fellowship by the Alexander von Humboldt Foundation, and the Hans Fischer Fellow by the Institute of Advanced Study of the Technical University of Munich. He was a recipient of the Best Paper Awards at the VLSI Test Symposium (VTS) in 2013 and IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems in 2015. He served as a Distinguished Visitor of the IEEE Computer Society for 2013-2015, the Chair of the IEEE Computer Society Tainan Chapter for 2013-2015, and the Chair of the ACM SIGDA Taiwan Chapter for 2014-2015. Currently he serves as an ACM Distinguished Speaker, a Distinguished Lecturer of the IEEE CAS Society, and Associate Editor of the ACM Journal on Emerging Technologies in Computing Systems, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, and IEEE Transactions on Very Large Scale Integration Systems, Guest Editor of IEEE Design & Test of Computers, and the Technical Program Committees of major conferences, including DAC, ICCAD, DATE, ASP-DAC, ISPD, ICCD, etc.
Title: Bridging Design and Technology Gaps for Manufacturability, Reliability, and Security
Abstract: As the semiconductor industry enters the era of extreme scaling (14nm, 11nm, and beyond), IC design and manufacturing challenges are exacerbated, due to the adoption of multiple patterning and other emerging lithography technologies such as EUV, DSA, and EBL. Meanwhile, new ways of equivalent scaling such as 2.5D/3D IC have gained tremendous interest and initial industry adoption, and new devices such as nanophotonics are making their headways to break the interconnect scaling bottleneck. Furthermore, hardware security has become a major concern due to fab outsourcing, extensive IP reuse, etc. thus unique identification/authentication and various IP protection schemes are in high demand. This talk will discuss some key challenges and recent results on how to bridge the design and technology gaps for manufacturability, reliability, and security in extreme scaling and beyond.
Bio: David Z. Pan received his B.S. degree from Peking University, and his M.S. and Ph.D. degrees from University of California, Los Angeles (UCLA). From 2000 to 2003, he was a Research Staff Member with the IBM T. J. Watson Research Center, Yorktown Heights, NY. He has been an Assistant Professor (2003-2008), Associate Professor with tenure (2008-2013), Full Professor (2013-), and Engineering Foundation Professor (2014-) with the Department of Electrical and Computer Engineering, The University of Texas at Austin. His research interests include cross-layer nanometer IC design for manufacturability/reliability, new frontiers of physical design, and CAD for emerging technologies such as 3D-IC, bio, and nanophotonics. He has published over 230 refereed journal and conference papers, and is the holder of 8 U.S. Patents.
He has served as a Senior Associate Editor of ACM Transactions on Design Automation of Electronic Systems (TODAES) and an Associate Editor of four IEEE journals, including IEEE Transactions on Computer Aided Design of Integrated Circuits and Systems (TCAD, 2006-2011), IEEE Transactions on Very Large Scale Integration Systems (TVLSI, 2007-present), IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I, 2008-2009), and IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS-II, 2006-2007). He is also an Associate Editor of Science China Information Science (SCIS), Journal of Computer Science and Technology (JCST), and the IEEE CAS Society Newsletter (2007-present). He has served as the IEEE CANDE Committee Chair, Program/General Chair of ISPD 2007/2008, TPC Vice-Chair/Chair of ASP-DAC 2016/2017, Tutorial Chair of DAC 2014, Workshop Chair of ICCAD 2015, and TPC Subcommittee Chair for DAC, ICCAD, ASPDAC, ISLPED, ICCD, ISCAS, among others. He is a working group member of the International Technology Roadmap for Semiconductor (ITRS). He has also served as an advisor or consultant to various companies including Cadence, Cooley LLP, Fish & Richardson, Pyxis, and Tabula.
He has received a number of awards for his research contributions and professional services, including the SRC 2013 Technical Excellence Award, DAC Top 10 Author in Fifth Decade, DAC Prolific Author Award, ASP-DAC Frequently Cited Author Award, 12 Best Paper Awards (ISPD 2014, ICCAD 2013, ASPDAC 2012, ISPD 2011, IBM Research 2010 Pat Goldberg Memorial Best Paper Award in CS/EE/Math, ASPDAC 2010, DATE 2009, ICICDT 2009, SRC Techcon in 1998, 2007, 2012 and 2015) and 11 other Best Paper Award nominations at DAC/ICCAD/ASPDAC/ISPD, Communications of the ACM Research Highlights (2014), ACM/SIGDA Outstanding New Faculty Award (2005), NSF CAREER Award (2007), SRC Inventor Recognition Award three times, IBM Faculty Award four times, UCLA Engineering Distinguished Young Alumnus Award (2009), UT Austin RAISE Faculty Excellence Award (2014), ISPD Routing Contest Awards (2007), eASIC Placement Contest Grand Prize (2009), ICCAD’12 and ICCAD’13 CAD Contest Awards, among others. He is an IEEE Fellow.
Title: The hare, the tortoise and the race for the next electronic switch
Abstract: The future of CMOS is at crossroads. On the one hand power dissipation limits arbitrary increase in clock speeds, on the other energy efficient approaches to computing often carry the penalty of slow operations. I will discuss opportunities with adaptive oxides, particularly strongly correlated semiconductors for future information processing and storage, their use in neuromorphic computing and a critical comparison to existing computing technologies. Slow glassy dynamics inherently present in correlated semiconductors may present an opportunity for emerging research directions in autonomous intelligence and I will consider this problem in some detail.
Bio: Dr. Ramanathan was on the research staff at Components Research, Intel, for over three years and was most recently a member of the Applied Physics faculty at Harvard University (2006 – 2015).
Shriram Ramanathan received his undergraduate degree in Metallurgy from IIT Madras, his M.S. in Materials Engineering from the University of Houston and a Ph.D. in Materials Science and Engineering from Stanford University in 2002.Dr. Ramanathan’s research interests are in materials sciences of complex oxides, strongly correlated matter and their applications in solid state.
Title: Spin as State Variable for Computation: Prospects and Perspectives
Abstract: Recent experiments on spin devices like magnetic tunnel junctions (MTJ's), domain wall magnets (DWM) and spin valves have led to the possibility of having very high density on-chip memories and logic. While the possibility of having on-chip spin transfer torque memories is close to reality, several questions still exist regarding the energy benefits of spin as the state variable for logic computation. Latest experiments on lateral spin valves (LSV) have shown switching of nano-magnets using spin-polarized current injection through a metallic channel such as Cu. Lateral spin valves with multiple input magnets connected to an output magnet using metal channels or domain wall magnetic strips can be used to mimic "neurons" . The spin-based neurons can be integrated with CMOS and other devices like domain wall magnetic strips or PCM’s to realize ultra low-power data processing hardware based on neural networks (NN), and are suitable for different classes of applications like, cognitive computing, programmable Boolean logic and analog and digital signal processing. In this talk I will first discuss the advantages of using spin (as opposed to charge) as state variable for both memory and logic and then present how a cellular array of magneto-metallic neurons, operating at terminal voltages ~20mV, can do efficient analog computation for applications such as image sensing and processing.
Bio: Kaushik Roy received B.Tech. degree in electronics and electrical communications engineering from the Indian Institute of Technology, Kharagpur, India, and Ph.D. degree from the electrical and computer engineering department of the University of Illinois at Urbana-Champaign in 1990. He was with the Semiconductor Process and Design Center of Texas Instruments, Dallas, where he worked on FPGA architecture development and low-power circuit design. He joined the electrical and computer engineering faculty at Purdue University, West Lafayette, IN, in 1993, where he is currently Edward G. Tiedemann Jr. Distinguished Professor. His research interests include spintronics, device-circuit co-design for nano-scale Silicon and non-Silicon technologies, low-power electronics for portable computing and wireless communications, and new computing models enabled by emerging technologies. Dr. Roy has published more than 600 papers in refereed journals and conferences, holds 15 patents, graduated 60 PhD students, and is co-author of two books on Low Power CMOS VLSI Design (John Wiley & McGraw Hill).
Dr. Roy received the National Science Foundation Career Development Award in 1995, IBM faculty partnership award, ATT/Lucent Foundation award, 2005 SRC Technical Excellence Award, SRC Inventors Award, Purdue College of Engineering Research Excellence Award, Humboldt Research Award in 2010, 2010 IEEE Circuits and Systems Society Technical Achievement Award, Distinguished Alumnus Award from Indian Institute of Technology (IIT), Kharagpur, Fulbright-Nehru Distinguished Chair, and best paper awards at 1997 International Test Conference, IEEE 2000 International Symposium on Quality of IC Design, 2003 IEEE Latin American Test Workshop, 2003 IEEE Nano, 2004 IEEE International Conference on Computer Design, 2006 IEEE/ACM International Symposium on Low Power Electronics & Design, and 2005 IEEE Circuits and system society Outstanding Young Author Award (Chris Kim), 2006 IEEE Transactions on VLSI Systems best paper award, 2012 ACM/IEEE International Symposium on Low Power Electronics and Design best paper award, 2013 IEEE Transactions on VLSI Best paper award. Dr. Roy was a Purdue University Faculty Scholar (1998-2003). He was a Research Visionary Board Member of Motorola Labs (2002) and held the M.K. Gandhi Distinguished Visiting faculty at Indian Institute of Technology (Bombay). He has been in the editorial board of IEEE Design and Test, IEEE Transactions on Circuits and Systems, IEEE Transactions on VLSI Systems, and IEEE Transactions on Electron Devices. He was Guest Editor for Special Issue on Low-Power VLSI in the IEEE Design and Test (1994) and IEEE Transactions on VLSI Systems (June 2000), IEE Proceedings -- Computers and Digital Techniques (July 2002), and IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2011). Dr. Roy is a fellow of IEEE.
Title: Integrated Magnetics and Multiferroics for Compact and Power Efficient Sensing, Memory, Power, RF and Microwave Electronics
Abstract: The coexistence of electric polarization and magnetization in multiferroic materials provides great opportunities for realizing magnetoelectric coupling, including electric field control of magnetism, or vice versa, through a strain mediated magnetoelectric interaction effect in layered magnetic/ferroelectric multiferroic heterostructures. Strong magnetoelectric coupling has been the enabling factor for different multiferroic devices, which however have been elusive, particularly at RF/microwave frequencies. In this presentation, I will cover the most recent progress on different RF/microwave magnetic and multiferroic heterostructures and devices, including power efficient and non-volatile voltage control of magnetism, nanoelectromechanical system magnetoelectric sensors with picoTesla sensitivity by using FeGaB/AlN thin-film magnetoelectric heterostructures, new integrated GHz magnetic and multiferroic inductors based on solenoid structures with FeGaB/Al2O3 and FeCoB/Al2O3 multilayers exhibiting >150% enhanced inductance and quality factor ~20 at GHz frequencies over their air core counterparts, power efficient voltage tunable magnetoelectric inductors with inductance tunability of 50%~150% at GHz, etc. At the same time, we will demonstrate other tunable multiferroic devices, including multiferroic voltage tunable bandpass filters, tunable bandstop filters, tunable phase shifters, multiferroic antennas, and spintronics, etc. These novel voltage tunable RF multiferroic devices show great promise for applications in radio frequency integrated circuits.
Bio: Nian Sun is a professor at the Electrical and Computer Engineering Department, Northeastern University, and Director of the W.M. Keck Laboratory for Integrated Ferroics. He received his Ph.D. degree from Stanford University. Prior to joining Northeastern University, he was a Scientist at IBM and Hitachi Global Storage Technologies. Dr. Sun was the recipient of the NSF CAREER Award, ONR Young Investigator Award, the Søren Buus Outstanding Research Award, etc. His research interests include novel magnetic, ferroelectric and multiferroic materials, devices and subsystems. He has over 200 publications and over 20 patents and patent disclosures. One of his papers was selected as the “ten most outstanding full papers in the past decade (2001~2010) in Advanced Functional Materials”. Dr. Sun has given over ~100 plenary, keynote and invited presentations or seminars. He is an editor of IEEE Transactions on Magnetics, and a fellow of the Institute of Physics, and of the Institution of Engineering and Technology.
Title: Specialization at the end of technology scaling
Abstract: Dennard scaling ended several generations ago. Moore’s Law scaling is slowing down. Many new device technologies have been proposed over the years, but none ready to realistically supplant silicon CMOS. Power dissipation is the main performance limiter. What does this all mean for us chip designers? Is this doom and gloom? Or are we entering a golden age of chip design?
This talk provides a broad overview of computer architecture and VLSI research activities at Harvard — highly energy-constrained RoboBees; a pre-RTL accelerator design tool called Aladdin; profiling Google’s datacenter to motivate hardware acceleration for future server SoCs; and a co-design framework for neural network accelerators. A common theme for all of these projects is the importance of specialized hardware acceleration to improve performance and energy efficiency, where cross-layer innovations in software, computer architecture, and chip design can meet the demands of new computing devices and applications on the horizon.
Bio: Gu-Yeon Wei is Gordon McKay Professor of Electrical Engineering and Computer Science at the John A Paulson School of Engineering and Applied Sciences at Harvard University. He received his BS, MS, and PhD degrees all in electrical engineering from Stanford University in 1994, 1997, and 2001, respectively. After an eighteen month stint at a high-speed links startup in Oregon, he joined the Harvard faculty in 2002. His research interests span a broad range of topics in mixed-signal and digital circuits and systems, computer architecture, design tools, low- and high-voltage power converters, robotics, and more.
Title: From green compute to green cloud
Abstract: As cloud computing become more and more popular, more large scale datacenters are built around the world. How to make datacenter more energy efficient become a challenges for all datacenter operators and cloud service providers. There many factors for green datacenters: compute is a major part of it. Intel has been a leading provider of server technology with focus on improving performance/watt for every generations of Xeon processor family. More overall, Intel has been promoting “server as a sensor” for datacenter management, so that we can apply the same principles of IOT (Internet of Things) for datacenter management to achieve energy efficient datacenter management. This talk will summarize Intel’s effort to make compute greener and make datacenter greener.
Bio: Dr. Jackson is the General Manager of Intel Asia and Pacific R&D Ltd. and Intel Software and Services Group (SSG) PRC. Dr. He joined Intel in 1995, served in various leadership roles within Intel IT and Intel Labs, DCG, and SSG. In recent years, Dr. He focused on enterprise and cloud solution evangelization, a key driver of Intel Cloud Builder Program in China and an Advisor to Open Data Alliance (ODCA). Dr. He has extensive experience working with enterprise, Telco, and IPDC customers in China. He served as Intel’s representative at several standards groups (OASIS, WS-I, DMTF, etc.). He also deeply involved in healthcare vertical. As the Intel rep, Dr. He led to definition of Reginal Healthcare Information System (RHTS) blueprint in China. He also served on China Senior Care Expert Committee. Dr. He has been active in open source solutions for cloud and big data. He initiated China Open Source Cloud League （COSCL） and led Intel/Cloudera collaboration on big data solutions for customers in China. Dr. He is well published including a book on future computing models and is a seasoned technical speaker. He received Ph.D. and MBA from the University of Hawaii.
Title: GaN based technologies for the next generation power applications
Abstract: Recently GaN power devices attracted a lot of attentions, for high power density and high efficiency applications. People predicted GaN could be one of the dominated technologies in the future power device market, just like what has occurred in lighting and microwave industries. Meantime, there are still some challenges for the mass production of GaN power devices, like the material cost, manufacturing yield and device reliabilities. In this talk, we would like to review the latest progress in this field and introduce SITRI’s GaN material and device R&D and prototyping platform.
Bio: Dr. Li Yuan is an expert with years of experience in the field of GaN power electronic industry. He developed the first MD/KMC program for GaN process modeling, the first normally-off GaN tunnel FET and China’s first 8-inch based GaN-on-Si power transistor. He participated in Singapore Thematic Strategic Research Programme (TSRP) projects as principal investigator and project leader. As one part of the Chinese National Science and Technology Major Project, he led the GaN power device program in Skysilicon. He contributed to more than 10 patents and 30 publications.
Dr. Li Yuan received a B.S. degree in Department of Microelectronics, Peking University in 2007. From 2007 to 2011, he studied in Hong Kong University of Science and Technology (HKUST) and obtained the Ph.D degree in 2011. From October 2011 to June 2013, he was a scientist in Institute of Microelectronics (IME), A*STAR, Singapore. In July 2013, he joined Skysilicon Co., LTD., as the leader of the Advanced Power Technology Research & Development Department. In March 2016, he joined SITRI to be the Director of Compound Semiconductor.
Title: Circuit Design in Nano-Scale CMOS Technologies
Abstract: CMOS technology scaling has followed Moore’s law well into the nano-scale regime now. The technology scaling is no longer just about geometric reduction but more about innovation in the use of new materials and transistor architectures. Relentless feature size reduction along with the innovations in transistor architecture and new material have created both challenges and opportunities for circuit designers to fully realize the technology scaling benefits. In this talk, an overview on the technology scaling will first be presented. The talk will then explore many advanced circuit design techniques that are key to achieve product-level scaling benefits. It will start with SRAMs, the work-horse for embedded memories. The state-of-the-art read-write-assist (RWA) techniques in SRAMs will be discussed for achieving adequate margins for low-voltage operation. Analog and mixed signal (AMS) circuits are long considered “not scalable” due to many unique design requirements and process sensitivities. In this talk, several novel digital-assist techniques are explored to illustrate how they can help achieve excellent power, performance, and area scaling in some common AMS circuits such as phase-lock-loop (PLL) and high-speed serial IO. Adaptive design concept has become a focal point in advanced circuits today to augment the process variations. A couple of design examples will be given to demonstrate the benefits of these advanced circuit techniques. To further improve system-level performance, more intelligent integration schemes are becoming more important. Again, real product examples, including integrated-voltage-regulator and in-package-memory, will be given on how they can help address the power/performance challenges at system-level. In conclusion, as CMOS technology scaling continues, novel circuit topologies and integration schemes will play an increasingly more important role in driving the power and performance scaling for future products.
Bio: Kevin Zhang is a Vice President of Technology and Manufacturing Group and an Intel Fellow at Intel Corporation. He is responsible for advanced circuit technology development for the company's future products. Zhang oversees the development of process design rules, circuit & device modeling, digital circuit libraries, key analog and mixed-signal circuits, high-speed I/O and embedded memories. Zhang has published more than 60 papers at international conferences and in technical journals and is the editor of Embedded Memory for Nano-Scale VLSIs, published by Springer in 2009. He holds more than 50 U.S. patents in the field of integrated circuit technology. Zhang is 2016 ISSCC Program chair and also serves on IEEE VLSI Executive Committee. Zhang is a Fellow of the Institute of Electrical and Electronics Engineers. He received his bachelor's degree from Tsinghua University in Beijing in 1987 and his Ph.D. from Duke University in 1994, both in electrical engineering.